Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures

ABSTRACT

A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.

This patent application is a Divisional Application and claims thePriority Date of a co-pending application Ser. No. 12/319,188 filed onDec. 31, 2008 by a common Inventor of this application. The Disclosuresmade in the patent application Ser. No. 12/319,188 are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the device configuration andmanufacturing methods for fabricating the semiconductor power devices.More particularly, this invention relates to an improved and novelmanufacturing process and device configuration for reducing the gate todrain coupled charges (Qgd) while providing a drain to source currentpath for preventing a drain to source resistance.

2. Description of the Related Art

In order to increase the switching speed of a semiconductor powerdevice, it is desirable to reduce the coupling charges between the gatesand drain Qgd such that a reduction of a gate to drain capacitance Crsscan be reduced. However, conventional device as shown in FIG. 1 has alarge amount of coupling charges Qgd between the gates and drain due tothe direct coupling between the sidewalls of the trench gates and thedrain. Specifically, Kobayashi discloses in a U.S. Pat. No. 6,888,196entitled “Vertical MOSFET reduced in Cell Size and Method of Producingthe Same” a vertical MOSFET device as that shown in FIG. 1.

In order to reduce the capacitance Crss, a double poly gates and doublegate oxide layers (a thick gate oxide on trench bottom) formed in trenchwith lower poly gate connected to source are disclosed in U.S. Pat. Nos.7,091,573 and 7,183,610. However, formation of the device structures isvery complicate and expensive.

Therefore, a need still exists in the art of power semiconductor devicedesign and manufacture to provide new manufacturing method and deviceconfiguration in forming the semiconductor power devices such that theabove discussed problems and limitations can be resolved.

SUMMARY OF THE PRESENT INVENTION

It is therefore an aspect of the present invention to provide a new andimproved semiconductor power device by forming P* dopant regionssurrounding the lower portions of the gate sidewalls to decouple thegate from the drain such that the coupling charges between the gate andthe drain can be reduced. Furthermore, a N* dopant region is formedright below the trench bottom to provide a current path between thedrain to the source such that the decoupling P* dopant regions will notinadvertently increase the drain to source resistance but Crss can besignificantly reduced to a capacitance that is about half or even lowerwhen compared with the capacitance of the conventional devices becausethe Crss will be mainly determined by trench width in the presentinvention when compared with the conventional device as shown in FIG. 1.

Another aspect of this invention is to form an improved MOSFET device byforming P* dopant regions surrounding the lower portions of the gatesidewalls to reduce the gate-to-drain coupling charges and N* regionsbelow the bottom of the trenches to provide a drain to current path.Furthermore, the improved MOSFET device is formed with thicker oxidelayer at the bottom of the trenched gate such that the gate to draincapacitance can be reduced. The performance of the device is improvedwith reduced Qgd by reducing the coupling areas between the gates to thedrain. The drain to source resistance is reduced with a current pathprovided by the N* dopant regions below the bottom of the trenches.

Briefly in a preferred embodiment, this invention discloses a trenchedsemiconductor power device comprising a plurality of trenched gatessurrounded by source regions near a top surface of a semiconductorsubstrate encompassed in body regions. The trenched semiconductor powerdevice further includes tilt-angle implanted body dopant regionssurrounding a lower portion of trench sidewalls for reducing agate-to-drain coupling charges Qgd between the trenched gates and adrain disposed at a bottom of the semiconductor substrate. The trenchedsemiconductor power device further includes a source dopant regiondisposed below a bottom surface of the trenched gates for functioning asa current path between the drain to the source for preventing aresistance increase caused by the body dopant regions surrounding thelower portions of the trench sidewalls. In an exemplary embodiment, eachof the trenched gates has a thicker oxide layer on sidewalls of a lowerportion of the trenched gates and a thinner oxide layer on sidewalls atan upper portion of the trenched gates. In another exemplary embodiment,the semiconductor power device further comprises a metal oxidesemiconductor field effect transistor (MOSFET) device. In anotherexemplary embodiment, the semiconductor power device further comprisinga N-channel MOSFET device wherein the body dopant regions comprisingP-type tilt-angle implanted regions surrounding the lower portion of thetrench sidewalls and the source dopant regions below the trenched gatescomprising N-dopant regions disposed in an N-type epitaxial layer. Inanother exemplary embodiment, the semiconductor power device furthercomprising a P-channel MOSFET device wherein the body dopant regionscomprising N-type tilt-angle implanted regions surrounding the lowerportion of the trench sidewalls and the source dopant regions below thetrenched gates comprising P-dopant regions disposed in an P-typeepitaxial layer. In another exemplary embodiment, the trenchedsemiconductor power device further includes an insulation layeroverlaying a top surface of the semiconductor substrate having aplurality of source/body contact trenches opened therethrough extendedto aid body regions through the source regions wherein the source/bodycontact trenches are filled with a contact meal plug composed oftungsten for electrically contacting to the source/body regions and bodyregions covered by the insulation layer. In another exemplaryembodiment, the trenched semiconductor power device further includes acontact dopant regions disposed in the body regions below thesource/body contact trenches constituting heavily body dopant regionsfor enhancing a contact with the contact metal plugs. In anotherexemplary embodiment, the trenched semiconductor power device furtherincludes a contact enhancement layer comprising a low resistance metalayer covering the insulation layer for contacting to the contact metalplugs for providing a larger contact area to a source metal layerdisposed on top of the contact enhancement layer for reducing aresistance between the source metal layer and the contact metal plugscontacting the source regions and body regions. In another exemplaryembodiment, the trenched semiconductor power device further includes asource metal layer comprising a patterned metal layer disposed on top ofthe insulation layer for electrically contacting to the metal plugsfilling the contact trenches for electrically connected to the sourceregions and body regions. In another exemplary embodiment, the trenchedsemiconductor power device further includes a gate pad layer comprisinga patterned metal layer disposed on top of the insulation layer forelectrically contacting to the metal plugs filling the contact trenchesfor electrically connected to the trenched gates.

This invention further discloses a method for manufacturing a trenchedsemiconductor power device on a semiconductor substrate. The methodfurther includes steps of: 1) opening a plurality of trenches from a topsurface of the semiconductor substrate; and 2) carrying out a tilt-anglebody-dopant implantation through sidewalls of trenches to form bodydopant regions surrounding sidewalls of the trenches followed bycarrying out a vertical source dopant implant to form a source dopantregion below a bottom surface of the trenches. In an exemplaryembodiment, the step of carrying out the tilt-angle body dopantimplantation through the sidewalls of the trenches further comprising astep of carrying out a tilt angle body dopant implantation with atilt-angle ranging between 4 to 45 degrees. In another exemplaryembodiment, the method further includes a step of growing a screen oxidelayer on the sidewalls of the trenches as a protection layer for thesidewalls before carrying out the step of tilt angle body dopantimplantation through the sidewalls of the trenches. In another exemplaryembodiment, the step of opening a plurality of trenches in thesemiconductor substrate further comprising a step of opening thetrenches in a N-type silicon substrate and the step of carrying out thetilt angle body dopant implantation further comprising a step ofcarrying out tilt angle boron implantation through the sidewalls of thetrenches into the N-type silicon substrate to form the body dopantregions surrounding the sidewalls of the trenches. In another exemplaryembodiment, the step of opening a plurality of trenches in thesemiconductor substrate further comprising a step of opening thetrenches in a N-type silicon substrate and the step of carrying out avertical source dopant implant further comprising a step of carrying outthe source dopant implant of arsenide ions to form the source dopantregion below the bottom surface of the trenches. In another exemplaryembodiment, the method further includes a step of growing a gate oxidelayer on the sidewalls and the bottom surface of the trenches anddepositing a gate dielectric layer into the trenches to form thetrenched gates. In another exemplary embodiment, the method furtherincludes a step of growing a gate oxide layer on the sidewalls of thetrenches; and the method further includes a step of forming a bottomgate oxide on the bottom surface of the trenches having a greaterthickness than the gate oxide on the sidewalls followed by depositing agate dielectric layer into the trenches to form the trenched gates. Inanother exemplary embodiment, the method further includes a step offorming body regions and source regions encompassed in the body regionssurrounding the trenched gates in the semiconductor substrate andcovering semiconductor substrate with an insulation layer followed byopening a plurality of contact trenches through the insulation layer forfilling the contact trenches with contact metal plugs with a some of themetal plugs contacting the body regions and source regions and othercontact plugs contacting the trenched gates. And the method furtherincludes a step of depositing a metal layer on top of the insulationlayer contacting the metal plugs and patterning the metal layer into asource metal and a gate pad. In another exemplary embodiment, the methodfurther includes a step of forming body regions and source regionsencompassed in the body regions surrounding the trenched gates in thesemiconductor substrate and covering semiconductor substrate with aninsulation layer followed by opening a plurality of contact trenchesthrough the insulation layer for filling the contact trenches withcontact metal plugs with a some of the metal plugs contacting the bodyregions and source regions and other contact plugs contacting thetrenched gates. And the method further includes a step of depositing alow resistance metal layer on top of the insulation layer for enhancinga contact to the metal plugs and forming a metal layer on top of the lowresistance metal layer contacting the metal plugs through the lowresistance metal layer and patterning the metal layer into a sourcemetal and a gate pad. In another exemplary embodiment, the methodfurther includes a step of implanting a contact dopant region throughthe contact trenches before depositing the contact metal plugs into thecontact trenches to enhance an electrical contact between the source andbody regions to the contact metal plugs.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is cross sectional view of a conventional trenched MOSFET powerdevice with reduced gate-to-drain capacitance and reduced epitaxialresistivity.

FIGS. 2 to 5 are four alternate embodiments of the present invention ofa MOSFET device implemented with dopant regions surrounding the lowerportions of the sidewalls and the bottom of the trenched gates to reducethe Qgd and to provide a drain to source current path.

FIGS. 6A to 6G-2 are a serial cross sectional views for describing themanufacturing processes to provide a trenched MOSFET device of thepresent invention with dopant regions surrounding the lower portions ofthe sidewalls and the bottom of the trenched gates to reduce the Qgd andto provide a drain to source current path.

DETAILED DESCRIPTION OF THE METHOD

Referring to FIG. 2 for a side cross sectional view of a MOSFET device100 formed on a N+ substrate 105 supporting an N-epitaxial layer 110with trenched polysilicon gates 130. Each of these trenched gates 130 ispadded by a gate oxide layer 125. A plurality of P-body regions 135disposed on the upper portion of the epitaxial layer 110 surround thetrenched gates 130. The body regions 135 further encompassed sourceregions 140 formed near the top surface of the epitaxial layer 110surrounding the trenched gates 130. An oxide insulation layer 145covering the top surface with contact openings right above the contactenhancing dopant regions 150 are opened through the insulation layer toallow for the metal contact layer 170 to physically contact thesource/body regions through a resistance reduction layer 158 to thecontact enhancing regions 150. The contact trenches 160 are filled withtungsten contact plugs padded with a barrier layer 160′ composed ofTi/TiN. The resistance reduction layer 158 is composed of a lowresistance metal layer such as a Ti or Ti/TiN layer. The contact metallayer 170 is further patterned to function as source metal and toprovide a gate pad (not specifically shown) to contact the, gate. Thecontact metal layer, e.g., the source metal layer 170 may be composed ofAlCu, AlSiCu or copper.

For the purpose of reducing the Qgd, the bottom portion of the sidewallsof the trenched gates 130 is surrounded by P-dopant regions 115.Furthermore, the central portions underneath the bottom of the trenchedgates are formed with an N-doped regions 120 below each trenched gates130. The Qgd is reduced with the P* dopant regions 115 while the N*dopant regions 120 under the trench bottom provide a current path ofdrain to source thus prevent an inadvertent increase of the resistance.Furthermore, by reducing the Qgd, the capacitance Crss may be reduced tohalf of the original capacitance or even lower compared to thecapacitance of the conventional devices.

FIG. 3 shows a side cross sectional view of an alternate MOSFET device100′ with similar device configuration as the MOSFET 100 of FIG. 2. Theonly difference is that the MOSFET 100′ does not include tungstencontact plugs and the resistance reduction metal layer 158 as thatimplemented in the MOSFET device shown in FIG. 2. The source metal layer170 composed of AlCu, AlSiCu or copper is directly filled into contacttrenches padded with a barrier layer 160′ composed of Ti/TiN, Co/TiN orTa/TiN . Again, the MOSFET device 100′ has P* dopant regions 115 toreduce the Qgd and also the N* dopant regions underneath the trenchedgates 130 thus providing a drain to source current path to reduce thedrain to source resistance.

FIG. 4 shows a side cross sectional view of another alternate MOSFETdevice 100″ with similar device configuration as the MOSFET 100 of FIG.2. The only difference is that the MOSFET 100″ is implemented withtrenched gate 130 padded with a bottom oxide layer 125′ that has greaterthickness than the gate oxide layer 125 on the sidewalls of thetrenches. The greater thickness of the bottom oxide layer 125′ furtherreduces a gate-to-drain coupling capacitance thus improving theswitching speed of the MOSFET device 100″.

FIG. 5 shows a side cross sectional view of another alternate MOSFETdevice 100″′ that has a device configuration similar to that of theMOSFET 100′ shown in FIG. 3. The only difference is that the MOSFET100″′ is implemented with trenched gate 130 padded with a bottom oxidelayer 125′ that has greater thickness than the gate oxide layer 125 onthe sidewalls of the trenches. The greater thickness of the bottom oxidelayer 125′ further reduces a gate-to-drain coupling capacitance thusimproving the switching speed of the MOSFET device 100″′.

Similar to the MOSFET 100 and 100′, the MOSFET devices 100″ and 100″′have P* dopant regions 115 surrounding the lower portion of the trenchsidewalls to reduce the Qgd. The MOSFET devices 100″ and 100″′ furtherhave the N* dopant regions underneath the trenched gates 130 thusproviding a drain to source current path to reduce the drain to sourceresistance.

Referring to FIGS. 6A to 6G-1 for a series of cross sectional views toillustrate the processing steps for manufacturing a MOSFET device asshown in FIGS. 2. In FIG. 6A, an oxide deposition process is firstperformed to deposit an oxide layer 108 on top of an N+ siliconsubstrate 105 supporting an N-type epitaxial layer 110 thereon. A trenchmask (not shown) is applied to open a plurality of trenches 109 in anepitaxial layer 110 by applying a dry oxide etch to open a plurality ofetch windows through the oxide layer 108 followed by a dry silicon etchto open the trenches into greater depth into the epitaxial layer 110. InFIG. 6B, a sacrificial oxide layer is grown (not shown) and removed torepair the sidewall surface of the trenches damaged by the trenchetching process. A screen oxide layer 111 is grown for preventingdamages caused by an ion implantation process. Then a boron angular ionimplant is carried out to form the P* regions 115 around the sidewallsof the trenches 109 and in the epitaxial layer 110 below the bottomsurface of the trenches 109. In FIG. 6C, a vertical ion implant iscarried out with N-type ions such as arsenic or phosphorus ions to formN* regions 120 in a region vertically below the bottom surface of thetrenches 109.

In FIG. 6D, the screen oxide layers 108 and 111 are removed and a gateoxide layer 125 is grown to cover the sidewalls and the bottom of thetrenchs 109. A doped polysilicon layer 130 is deposited to fill thetrenches followed by etching back the polysilicon layer above the topsurface of the trenches. In FIG. 2E, a body dopant implant is performedfollowed by a body dopant diffusion process to form the body regions135. Then, a source mask (not shown) is applied to carry out a sourcedopant implant followed by a source dopant diffusion process to form thesource regions 140 near the top surface at the upper portion of the bodyregions 135. In FIG. 6F, the source mask (not shown) is removed followedby depositing a top oxide insulation layer 145. Then a contact mask (notshown) is applied to perform a dry oxide etch followed by a silicon etchto open a plurality of source/body contact trenches 148 and gate contacttrenches (not shown) through the top insulation layer 145. A BF2 implantis carried out to form the contact dopant regions 150 below the contacttrenches 148. In FIG. 6G-1, a barrier layer 155 covering the sidewallsand the bottom surface of the contact trenches and composed of Ti/TiN,Co/TiN, or Ta/TiN is formed. Then a contact metal layer 160 composed ofAlCu, AlSiCu, or Cu is formed on top of the barrier layer 155 and fillup the contact trenches 148. The metal layer 160 is then patterned toform the source metal and gate pads as part of the standard processingsteps. FIG. 6G-2 shown the processes carried out for another preferredembodiment. A barrier layer 155 composed of Ti/TiN is first depositedfollowed by depositing a tungsten layer 160 on top of the barrier layer155 to fill up the contact trenches. An etch back process is carried outto etch back the tungsten and Ti/TiN layers from the surface above thecontact trenches. Then a contact enhancement layer 158 composed of Ti orTi/TiN is formed to cover the contact trenches 160 and the top surfacesaround the contact trenches. A contact metal layer 170 is then formed ontop of the contact enhancement layer 158 wherein the contact enhancementlayer 158 provides an expanded contact surface area with the contactmetal layer 170 thus reducing the resistance of contact meal layer 170to the source/body regions through the trench contact 160.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artafter reading the above disclosure. Accordingly, it is intended that theappended claims be interpreted as covering all alterations andmodifications as fall within the true spirit and scope of the invention.

1. A method for manufacturing a trenched semiconductor power device on asemiconductor substrate comprising: opening a plurality of trenches froma top surface of said semiconductor substrate; and carrying out atilt-angle body-dopant implantation through sidewalls of trenches toform body dopant regions surrounding sidewalls of said trenches followedby carrying out a vertical source dopant implant to form a source dopantregion below a bottom surface of said trenches.
 2. The method of claim 1wherein: said step of carrying out said tilt-angle body dopantimplantation through said sidewalls of said trenches further comprisinga step of carrying out a tilt angle body dopant implantation with atilt-angle ranging between 4 to 45 degrees.
 3. The method of claim 1further comprising: growing a screen oxide layer on the sidewalls ofsaid trenches as a protection layer for said sidewalls before carryingout said step of tilt angle body dopant implantation through saidsidewalls of said trenches.
 4. The method of claim 1 wherein: said stepof opening a plurality of trenches in said semiconductor substratefurther comprising a step of opening said trenches in a N-type siliconsubstrate and said step of carrying out said tilt angle body dopantimplantation further comprising a step of carrying out tilt angle boronimplantation through said sidewalls of said trenches into said N-typesilicon substrate to form said body dopant regions surrounding saidsidewalls of said trenches.
 5. The method of claim 1 wherein: said stepof opening a plurality of trenches in said semiconductor substratefurther comprising a step of opening said trenches in a N-type siliconsubstrate and said step of carrying out a vertical source dopant implantfurther comprising a step of carrying out said source dopant implant ofarsenic ions to form said source dopant region below said bottom surfaceof said trenches
 6. The method of claim 1 further comprising: growing agate oxide layer on said sidewalls and said bottom surface of saidtrenches and depositing a gate conductive layer into said trenches toform said trenched gates.
 7. The method of claim 1 further comprising:growing a gate oxide layer on said sidewalls of said trenches; andforming a bottom gate oxide on said bottom surface of said trencheshaving a greater thickness than said gate oxide on said sidewallsfollowed by depositing a gate conductive layer into said trenches toform said trenched gates.
 8. The method of claim 6 further comprising:forming body regions and source regions encompassed in said body regionssurrounding said trenched gates in said semiconductor substrate andcovering semiconductor substrate with an insulation layer followed byopening a plurality of contact trenches through said insulation layerfor filling said contact trenches with contact metal plugs with a someof said metal plugs contacting said body regions and source regions andother contact plugs contacting said trenched gates; and depositing ametal layer on top of said insulation layer contacting said metal plugsand patterning said metal layer into a source metal and a gate pad. 9.The method of claim 6 further comprising: forming body regions andsource regions encompassed in said body regions surrounding saidtrenched gates in said semiconductor substrate and coveringsemiconductor substrate with an insulation layer followed by opening aplurality of contact trenches through said insulation layer for fillingsaid contact trenches with contact metal plugs with a some of said metalplugs contacting said body regions and source regions and other contactplugs contacting said trenched gates; and depositing a low resistancemetal layer on top of said insulation layer for enhancing a contact tosaid metal plugs and forming a metal layer on top of said low resistancemetal layer contacting said metal plugs through said low resistancemetal layer and patterning said metal layer into a source metal and agate pad.
 10. The method of claim 6 further comprising: implanting acontact dopant region through said contact trenches before depositingsaid contact metal plugs into said contact trenches to enhance anelectrical contact between the source and body regions to the contactmetal plugs.